Data transmission device and data reception device

ABSTRACT

As shown in FIG.  7 , a data receiver receives video data and audio data together with a frequency division parameter N that depends on the pixel clock of the video data and the sampling frequency of the audio data, and a count value CTS that is obtained by counting the period of the audio clock that has been subjected to frequency division by the frequency division parameter N, with the pixel clock, which are transmitted from a data transmitter, and subjects the pixel clock to frequency division by the count value CTS, phase-control the divided clock (s 501 ) in accordance with a phase comparison clock (s 505 ) that is obtained by dividing an audio clock (s 403 ) oscillated from a VCO ( 504 ) by the frequency division parameter N, thereby generating an audio clock (s 403 ). 
     Accordingly, the data transmitter and the data receiver can satisfactorily implement multiplexing of audio data and video data, and transmission of the multiplexed data using an existing DVI cable, with a simple structure.

TECHNICAL FIELD

The present invention relates to a data transmitter and a data receiver in a digital data transmission system in which a video signal source and a video display unit are connected, for example, through a DVI (Digital Video Interface) and, more particularly, to a data transmitter and a data receiver that can easily and satisfactorily transmit audio data through an existing interface for transmitting video data.

BACKGROUND ART

Recently, a standard that is referred to as DVI has been standardized for transmitting video data to a display unit in digital format when a video signal source such as a television tuner, a video player, or a personal computer device is connected to a video display unit such as a monitor receiver.

Details of the DVI standard are given in an embodiment which will be described later, but in brief, this DVI standard digitizes respective primary color signals R, G, and B of video data in units of pixels and transmits the digitized data to a display unit, thereby realizing transmission and display of high quality pictures. Further, the display unit can directly drive a display driver by the received video data in units of pixels, thereby achieving the display with a relatively simple processing structure.

However, since a cable which is defined according to the DVI standard basically transmits only video data, then when audio data are to be transmitted together with video data, the display unit should be connected to an audio output device such as a tuner, through an audio cable that is different from the DVI standard cable.

More specifically, considering a system configuration that transmits only video data, a video signal source 600 and a display unit 610 are connected with a DVI standard cable 620 as shown in FIG. 30, and video data that is encoded in accordance with the DVI standard is transmitted through the cable 620, whereby video data can be transmitted from the video signal source 600 to the display unit 610.

On the other hand, when video data and audio data are transmitted from a video/audio signal source 700 to a display unit 710 with speakers as shown in FIG. 31, the video/audio signal source 700 and the display unit 710 with speakers are connected by a DVI standard cable 620 and an audio signal cable 630 that is different from the cable 620, and the video data is transmitted through the DVI cable 620 while the audio data is transmitted through the audio signal cable 630. In this way, the video data that is outputted from the video/audio signal source 700 can be displayed on the display unit 710 with speakers while the sounds are outputted from speakers 711 and 712 that are attached to the display unit 710.

However, when the video data and the audio data are transmitted from the video/audio signal source 700 to the display unit 710 using the two separate cables for video data and audio data as shown in FIG. 31, the connection structure correspondingly becomes complicated. Therefore, it is more preferable that fewer cables should be used for connecting the devices.

As a technology of multiplexing video data and audio data to transmit the multiplexed data through one cable, a data transmission technology using a bus line has been conventionally standardized as IEEE (The Institute of Electrical and Electronics Engineers) 1394 scheme. When a bus line that is standardized according to IEEE1394 method is employed as a cable for connecting the devices, video data and audio data can be simultaneously transmitted through one cable. However, in order to perform data transmission using the IEEE1394 bus line, very complicated data processing is required, whereby a structure on a transmitting end for encoding data to be transmitted, or a structure on a receiving end for decoding data that is received via the bus line needs quite a large circuit construction, resulting in an increased cost.

Further, since the IEEE1394 method compressively encodes and multiplexes video data and audio data in view of the transmission rate or the like, the quality of picture is lower than the above-mentioned DVI standard that transmits only video data which is digitized in units of pixel.

When digitized audio data is to be transmitted together with video data, a clock for audio data should be transmitted together with a clock for video data, and accordingly a signal line for transmitting the audio clock is required. Further, as a high-speed signal is transmitted through the signal line for the audio clock transmission, jitter is adversely increased.

The present invention is made to solve the above-mentioned problems, and has for its object to provide a data transmitter that transmits audio data and data for generating an audio clock from a transmitting end using an existing interface for transmitting video data, and a data receiver that receives the audio data and the data for generating an audio clock, and generating the audio clock easily and satisfactorily, to reproduce the audio data on a receiving end using the existing interface.

DISCLOSURE OF THE INVENTION

According to Claim 1 of the present invention, there is provided a data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, this data processing unit includes: a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generates the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and the transmission audio clock is a clock having a frequency of 300 Hz or higher.

Therefore, video data and audio data can be simultaneously transmitted using a transmission line for transmitting video data with utilizing the existing construction for transmitting video data as it is. Further, a frequency division parameter N that makes the frequency of an audio clock obtained by the frequency division higher than 300 Hz and the count value CTS are transmitted from the transmitting end. Therefore, when an audio clock is generated on the receiving end, it is possible to reduce the synchronization-pull-in time, and even when the pixel clock or the audio data sampling frequency of the data is changed during the data receiving, it is possible to generate an audio clock that enables to reduce the time for synchronization pull-in reestablished.

According to Claim 2 of the present invention, there is provided a data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, this data processing unit includes: a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock that has been generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generates the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and the transmission audio clock is a clock having a frequency of 3000 Hz or lower.

Therefore, video data and audio data can be simultaneously transmitted through a transmission line for transmitting video data with utilizing the existing construction for transmitting video data as it is. Further, since the frequency division parameter N that makes the frequency of an audio clock obtained by the frequency division lower than 3000 Hz and the count value CTS are transmitted from the transmitting end, when an audio clock is generated on the receiving end, it is possible to generate an audio clock that enables to suppress clock jitter, resulting in high-quality audio data.

According to Claim 3 of the present invention, there is provided a data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, this data processing unit includes: a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock that has been generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generates the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and the transmission audio clock is a clock having a frequency that is 300 Hz or higher, and 3000 Hz or lower.

Therefore, video data and audio data can be simultaneously transmitted through a transmission line for transmitting video data with utilizing the existing construction for transmitting video data as it is. Further, since the frequency division parameter N that makes the frequency of an audio clock obtained by the frequency division higher than 300 Hz and lower than 3000 Hz and the count value CTS are transmitted from the transmitting end, when an audio clock is generated on the receiving end, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 4 of the present invention, when the pixel clock is 25.2/1.00 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 8( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2/1.001 MHz and audio data having the audio data sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 5 of the present invention, when the pixel clock is 25.2/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 8( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2/1.001 MHz and audio data having the audio data sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 6 of the present invention, when the pixel clock is 25.2/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 8( c).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2/1.001 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 7 of the present invention, when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 9.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 8 of the present invention, when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIGS. 10, 11, 12, 13, 14 and 15(a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 9 of the present invention, when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIGS. 15( b) and 16.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 25.2 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 10 of the present invention, when the pixel clock is 27 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 17( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 11 of the present invention, when the pixel clock is 27 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 17( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 12 of the present invention, when the pixel clock is 27 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 18.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 13 of the present invention, when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 19( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27×1.001 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 14 of the present invention, when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 19( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27×1.001 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 15 of the present invention, when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 19( c).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 27×1.001 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 16 of the present invention, when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 20( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 54.0 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 17 of the present invention, when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIGS. 20( b) and 21(a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 54.0 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 18 of the present invention, when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIGS. 21( b) and 22.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 54.0 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 19 of the present invention, when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 32 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=11648 and 210937≦CTS≦210938.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25/1.001 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 20 of the present invention, when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=17836 and CTS=234375.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25/1.001 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 21 of the present invention, when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=11648 and CTS=140625.

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25/1.001 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 22 of the present invention, when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 24( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 23 of the present invention, when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 24( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 24 of the present invention, when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 24( c).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 74.25 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 25 of the present invention, when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 25( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5/1.001 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 26 of the present invention, when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 25( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5/1.00 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 27 of the present invention, when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 25( c).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5/1.001 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 28 of the present invention, when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 26( a).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5 MHz and audio data having the sampling frequency of 32 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 29 of the present invention, when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 26( b).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5 MHz and audio data having the sampling frequency of 44.1 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 30 of the present invention, when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) have a relationship as shown in FIG. 26( c).

Therefore, when an audio clock is generated on the receiving end in cases where video data having the pixel clock of 148.5 MHz and audio data having the sampling frequency of 48 kHz are transmitted together, it is possible to generate an audio clock that enables to reduce the synchronization pull-in time, or suppress the clock jitter, thereby generating high-quality audio data.

According to Claim 31 of the present invention, there is provided a data receiver that receives video/audio data through a digital display connecting interface, including: a video/audio data separating unit for separating video data and transmission audio data from the video/audio data; and an audio clock generating unit for generating an audio clock as a reference clock for audio data, on the basis of a pixel clock as a reference clock for the video data and a frequency division parameter N that has been added to the transmission audio data, this audio clock generating unit includes: an oscillator that oscillates the audio clock in accordance with a control signal; a frequency dividing means for frequency dividing the pixel clock using a count value CTS included in the transmission audio data to generate a frequency division clock having a period that is CTS times longer than the pixel clock; and a phase control means for controlling the oscillator in accordance with the control signal that is generated on the basis of a difference in phase between the frequency division clock and a phase comparison clock that is obtained by dividing the audio clock by a frequency division parameter N.

Therefore, video data and audio data can be simultaneously transmitted through a transmission line for transmitting video data with utilizing the existing construction for transmitting video data as it is. Further, an audio clock that maintains synchronization can be generated on the receiving end.

According to Claim 32 of the present invention, the phase control means controls the oscillator on the basis of a difference in phase between the frequency division clock that is generated by the frequency dividing means and the phase comparison clock having a frequency that is nearest to 1000 Hz.

Therefore, when an audio clock is generated on the receiving end, it is possible to reduce the synchronization pull-in time, and suppress occurrence of jitter.

According to Claim 33 of the present invention, when the sampling frequency for the audio data is 44.1 kHz, the phase control means controls the oscillator on the basis of a difference in phase between the frequency division clock that is generated by the frequency dividing means, and the phase comparison clock having a frequency that is nearest to 900 Hz.

Therefore, when an audio clock is generated on the receiving end, it is possible to reduce the synchronization pull-in time and suppress occurrence of jitter. Further, commonality can be achieved among values of the frequency division parameter N, whereby the circuit design of the data receiver is simplified, resulting in reduction of the manufacturing cost of the receiver.

According to Claim 34 of the present invention, when the data sampling frequency of the audio data is 32 kHz or 48 kHz, and the pixel clock has a frequency other than 25.2/1.001 MHz, 25.022 MHz, 27.000 MHz, 27.0×1.001 MHz, 54.000 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.00 MHz, and 148.5 MHz, the frequency division parameter N (N is an integer) is decided such that the phase comparison clock that is obtained by dividing the pixel clock by the frequency division parameter N has a frequency nearest to 1000 Hz.

Therefore, even when a pixel clock other than the above pixel clocks is inputted, an audio clock that maintains synchronization can be generated on the receiving end. Further, the circuit design of the data receiver is simplified, thereby reducing the manufacturing cost of the receiver.

According to Claim 35 of the present invention, when the data sampling frequency of the audio data is 44.1 kHz, and the pixel clock has a frequency other than 25.2/1.001 MHz, 25.022 MHz, 27.000 MHz, 27.0×1.001 MHz, 54.000 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.001 MHz, and 148.5 MHz, the frequency division parameter N (N is an integer) is decided such that the phase comparison clock that is obtained by dividing the pixel clock by the frequency division parameter N has a frequency nearest to 900 Hz.

Therefore, even when a pixel clock other than the above pixel clocks is inputted, an audio clock that maintains synchronization can be generated on the receiving end. Further, the circuit design of the data receiver is simplified, thereby reducing the manufacturing cost of the receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an entire construction of a digital data transmission system according to a first embodiment of the present invention.

FIG. 2 is a diagram explaining an operation for superimposing audio data upon video data that is transmitted in DVI format.

FIG. 3 is a diagram illustrating an example of a digital audio data structure.

FIG. 4 is a block diagram illustrating a construction of a data transmitter according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating components for obtaining a frequency division parameter N and a count value CST in an audio data processing means of a data transmitter according to an embodiment of the present invention.

FIG. 6 is a block diagram illustrating a structure of a data receiver according to an embodiment of the present invention.

FIG. 7 is a block diagram illustrating a structure of an audio clock generation means of a data transmitter according to an embodiment of the present invention.

FIG. 8 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2/1.001 MHz according to an embodiment of the present invention, FIG. 8( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 8( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 8( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 9 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 32 kHz according to an embodiment of the present invention.

FIG. 10 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 44.1 kHz according to an embodiment of the present invention.

FIG. 11 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 44.1 kHz according to an embodiment of the present invention.

FIG. 12 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 44.1 kHz according to an embodiment of the present invention.

FIG. 13 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling clock is 44.1 kHz according to an embodiment of the present invention.

FIG. 14 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 44.1 kHz according to an embodiment of the present invention.

FIG. 15 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 44.1 kHz (FIG. 15( a)) and a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 48 kHz (FIG. 15( b)) according to an embodiment of the present invention.

FIG. 16 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 25.2 MHz and the audio sampling frequency is 48 kHz according to an embodiment of the present invention.

FIG. 17 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 27 MHz and the audio sampling frequency is 32 kHz (FIG. 17( a)) and in a case where the pixel clock is 27 MHz and the audio sampling frequency is 44.1 kHz (FIG. 17( b)) according to an embodiment of the present invention.

FIG. 18 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 27 MHz and the audio sampling frequency is 48 kHz according to an embodiment of the present invention.

FIG. 19 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 27.0×1.001 MHz according to an embodiment of the present invention, FIG. 19( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 19( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 19( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 20 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 54.0 MHz and the audio sampling frequency is 32 kHz (FIG. 20(a)), and a case where the pixel clock is 54.0 MHz and the audio sampling frequency is 44.1 kHz (FIG. 20( b)) according to an embodiment of the present invention.

FIG. 21 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 54.0 MHz and the audio sampling frequency is 44.1 kHz (FIG. 21( a)), and a case where the pixel clock is 54.0 MHz and the audio sampling frequency is 48 kHz (FIG. 21( b)) according to an embodiment of the present invention.

FIG. 22 is a diagram showing possible values of the frequency division parameter N in a case where the pixel clock is 54.0 MHz and the audio sampling frequency is 48 kHz according to an embodiment of the present invention.

FIG. 23 are diagrams showing possible values of the frequency division parameter N in a case where the pixel clock is 74.25/1.001 MHz according to an embodiment of the present invention, FIG. 23( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 23( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 23( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 24 are diagrams showing possible values of the frequency division parameter N when the pixel clock is 74.25 MHz according to an embodiment of the present invention, FIG. 24( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 24( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 24( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 25 are diagrams showing possible values of the frequency division parameter N when the pixel clock is 148.5/1.001 MHz according to an embodiment of the present invention, FIG. 25( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 25( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 25( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 26 are diagrams showing possible values of the frequency division parameter N when the pixel clock is 148.5 MHz according to an embodiment of the present invention, FIG. 26( a) showing a case where the audio sampling frequency is 32 kHz, FIG. 26( b) showing a case where the audio sampling frequency is 44.1 kHz, and FIG. 26( c) showing a case where the audio sampling frequency is 48 kHz.

FIG. 27 is a diagram showing recommendation parameters of the frequency division parameter N for respective pixel clocks and respective audio sampling frequencies according to an embodiment of the present invention.

FIG. 28 is a diagram showing recommendation parameters of the frequency division parameter N for respective pixel clocks and respective audio sampling frequencies according to an embodiment of the present invention.

FIG. 29 is a diagrams showing values of the frequency division parameter N, which provide the frequency of the phase comparison clock that is nearest to 1 kHz at respective pixel clocks in a case where the audio sampling frequency is 44.1 kHz according to an embodiment of the present invention.

FIG. 30 is a block diagram illustrating an entire construction of a conventional system for transmitting only video data.

FIG. 31 is a diagram for explaining problems of the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1

Hereinafter, an embodiment of the present invention will be described with reference to the figures.

A digital data transmission system according to this embodiment is adapted to transmit video data and audio data that are outputted from a video/audio signal source, such as a videocassette tape recorder/player, a video disk player, or a tuner, to a display unit such as a monitor receiver having a sound output function or a television receiver, through one transmission cable. Here, a cable that transmits data based on a standard which is referred to as DVI (Digital Visual Interface) is utilized for the transmission cable.

Initially, the digital data transmission system according to the embodiment will be described with reference to FIGS. 1 to 3.

FIG. 1 is a diagram illustrating an entire construction of a digital data transmission system according to this embodiment. In this figure, reference numeral 100 denotes a video/audio signal source such as a videotape recorder/player, a video disk player, and a tuner. Numeral 110 denotes a data transmitter that superimpose video data and audio data which are outputted from the video/audio signal source 100, and transmits the superimposed data to a DVI cable. Numeral 120 denotes a DVI cable. Numeral 130 denotes a data receiver that receives a video/audio data superimposed signal (video/audio signal) that has been transmitted through the DVI cable 120, and outputs video data and an analog audio data signal. Numeral 140 denotes a video/audio display unit that receives the video data and the analog audio signal from the data receiver 130, and performs video display and audio outputting. Each of connector portions (not shown) of the data transmitter 110 and the data receiver 130 to which the DVI cable 120 is connected is formed for example by a 24-pin connector, and the 24 pins of the connector of the data transmitter 110 and the 24 pins of the connector of the data receiver 130 are connected with the DVI cable 120.

According to this embodiment, in order to transmit audio data by the digital data transmission system having the above construction, transmission audio data is superimposed upon video data in DVI format, and then the obtained video/audio superimposed signal is transmitted from the data transmitter 110 to the data receiver 130 through the DVI cable 120, together with a horizontal blank sync signal or a pixel clock, as shown in FIG. 2. Further, when the audio data that has been transmitted with being superimposed upon video data is reproduced by the data receiver 130 as an analog audio signal, an audio clock as an audio data reference clock is needed. However, since the audio clock cannot be transmitted directly by the DVI cable 120, the data transmitter 110 adds additional information to the audio data, such as a frequency division parameter N that is used to divide the audio clock to obtain a transmission audio clock having a common multiple frequency between the pixel clock and the audio clock, and a count value CTS that is obtained by counting the period of the transmission audio clock with the pixel clock, and superimposes the transmission audio data including the additional information upon the video data, transmits the superimposed data to the data receiver 130, and then the data receiver 130 generates an audio clock that maintains the synchronization on the basis of the frequency division parameter N and the count value CTS as the additional information.

Hereinafter, a structure of video data in DVI format, which is transmitted through the DVI cable 120 is described with reference to FIG. 2. When video data is transmitted, B data (Blue data) shown in channel 0, G data (Green data) shown in channel 1, and R data (Red data) shown in channel 2 are transmitted by the corresponding channels, respectively, as 8 bits data per pixel, i.e., 24 bits data per pixel in total for the three channels. When pixel data are practically transmitted by the DVI cable 120, 8 bit data are converted into 10 bit data. Further, pixel data of each channel is transmitted in synchronization with the pixel clock.

In the DVI format, pixel data for each channel is not transmitted during horizontal blanking intervals and vertical blanking intervals, but data that is defined as a horizontal sync signal HSYNC or a vertical sync signal VSYNC, or various kinds of control data are transmitted. Therefore, the digital data transmission system according to this embodiment superimposes transmission audio data that is generated by processing audio data, upon the horizontal blanking interval of any channel (transmission channel for G data, shown by channel 1 in FIG. 2).

The audio data that is inputted in this embodiment is, for example, audio data that is packetized in accordance with IEC (International Electrotechnical Commission) 60958 standard as shown in FIG. 3. A packet (sub-frame) of data based on IEC60958 standard is composed of 32 bits as shown in FIG. 3. A 4-bit preamble is located at the head, the subsequent 24-bit section contains audio data of one sample (audio sample word), and last four bits are sub-codes (VUCP). Data of one sample that is composed of less than 24 bits (for example 16 bits) may be contained.

The structures of the data transmitter 110 and the data receiver 130 according to this embodiment, which transmits and receives video data upon which the above-mentioned transmission audio data are superimposed, will be described in detail with reference to FIGS. 4 to 7.

Initially, FIG. 4 is a block diagram illustrating the structure of the data transmitter in the digital data transmission system according to this embodiment, and FIG. 5 is a block diagram illustrating components for generating the frequency division parameter N and the count value CTS in an audio data processing means of the data transmitter.

In FIG. 4, numeral 201 denotes an audio data processing means that adds additional information to digital audio data that is outputted from the video/audio signal source 100, and superimposes the audio data upon video data to create transmission audio data s201 that is transmitted to the data receiver 130. Numeral 202 denotes a data storage means that temporarily stores the transmission audio data s201 that is created by the audio data processing means 201. Numeral 203 denotes a video/audio data superposition means that generates a timing signal using a horizontal blank sync signal and a pixel clock of video data which are outputted from the video/audio signal source 100, and superimposes the transmission audio data s201 stored in the data storage means 202 at a predetermined position in the horizontal blanking interval of the video data outputted from the video/audio signal source 100 using the generated timing signal, thereby generating a video/audio data superimposed signal s204. Numeral 204 denotes an input terminal for audio data. Numeral 205 denotes an input terminal for video data.

To the data transmitter 110 having the above-mentioned structure, digital audio data is inputted from an audio processing unit (not shown) of the video/audio signal source 100 through the audio data input terminal 204, while video data encoded in accordance with the DVI standard is inputted from a video processing unit (not shown) of the video/audio signal source 100 through the video data input terminal 205. The digital audio data is inputted to the audio data processing means 201, while the video data is inputted to the video/audio data superimposition means 203.

The audio data processing means 201 decides a frequency division parameter N on the basis of the pixel clock of video data and the sampling frequency of audio data that are outputted from the video/audio signal source 100, and counts the period of a transmission audio clock that is N times longer than the audio clock, which is obtained by performing frequency division of the audio clock using the frequency division parameter N, with the pixel clock, to obtain the count value CTS, and adds additional information, such as the frequency division parameter N and the count value CTS, to the audio data, thereby generating transmission audio data s201.

Components of the audio data processing means 201 for generating the frequency division parameter N and the count value CTS will be described with reference to FIG. 5. To simplify the figure, only flows of clocks are shown while flows of data are not shown.

The audio clock and the pixel clock inputted to the audio data processing means 201 are inputted to a frequency division parameter decision means 301. The frequency division parameter decision means 301 decides the frequency division parameter N on the basis of the sampling frequency of the audio data and the pixel clock, and outputs the decided parameter. It is assumed here that the audio clock has a frequency that is 128 times higher than the sampling frequency of audio data.

The frequency division parameter N is decided as follows: A table indicating the relationship among the pixel clock, the sampling frequency of audio data, and the frequency division parameter N is previously provided to the frequency division parameter decision means 301, and an appropriate value is selected from the table that is previously provided to the frequency division parameter decision means 301 in accordance with the audio clock and the pixel clock inputted to the frequency division parameter decision means 301. Though not shown, when the video/audio signal source 100 is a CD or a DVD, and the data transmitter 110 includes a control means for controlling the digital data transmission system, the control means can directly capture the sampling frequency of audio data and the pixel clock value from a predetermined area in the CD or DVD, and output the same to the frequency division parameter decision means 301 in the audio data processing means 201, and then the frequency division parameter decision means 301 can decide the value of the frequency division parameter N in accordance with the outputted values. The possible values of the frequency division parameter N and the table that is previously provided to the frequency division parameter decision means 301 will be described later.

The frequency division parameter N that has been decided by the frequency division parameter decision means 301 is inputted to the frequency division means 302. The frequency division means 302 performs frequency division of the audio clock using the frequency division parameter N, thereby to generate a transmission audio clock s302 having a period that is N times longer than the audio clock. Then, the period of the generated transmission audio clock s302 is counted with the pixel clock by a counter 303, and the obtained count value CTS is outputted.

Though not shown in FIG. 5, a header including the additional information, such as the frequency division parameter N and the counter value CTS which have been obtained as described above, and the length of processed data, is added to the audio data by the audio data processing means 201, and data transformation into a format which is suitable for data transmission, such as transformation into multi-bit data, thereby generating the transmission audio data s201. In FIG. 5, the frequency division parameter N and the counter value CTS are shown as being outputted from the audio data processing means 201, but this indicates that the frequency division parameter N and the counter value CTS are outputted with being added to the above-mentioned transmission audio data s201.

Then, the transmission audio data s201 that has been generated by the audio data processing means 201 is temporarily stored in the data storage means 202, and inputted to the video/audio data superimposition means 203 in accordance with a reading signal s202 that is synchronized with an audio data superimposition timing signal which is generated by the video/audio data superimposition means 203.

Then, the video/audio data superimposition means 203 generates a superimposition timing signal for audio data, using the horizontal blank sync signal and the pixel clock which are supplied from the video/audio signal source 100.

More specifically, the video/audio data superimposition means 203 starts counting the pixel clock when the horizontal blank sync signal is inputted, and then outputs the reading signal s202 to the data storage means 202 at a timing when a predetermined count of “n” (n is an arbitrary integer) has been reached. The transmission audio data s201 that is temporarily stored in the data storage means 202 is inputted from the data storage means 202 to the video/audio data superimposition means 203 in response to the reading signal s202 that is outputted from the video/audio data superimposition means 203, and is superimposed at a predetermined position in the horizontal blanking interval of video data. For example, when the horizontal frequency of video data is 15.75 kHz and the sampling frequency of audio data is 48 kHz, one horizontal scanning period of video data is about 63.5 μsec (=1/15.75 kHz) and one sampling period of audio data is about 20.8 μsec (=1/48 kHz). Therefore, when a process for transmitting 4 frames of audio data by one horizontal line is carries out once each time a process for transmitting 3 frames of audio data by one horizontal line is carries out several tens of times, data transmission can be performed without delay of the audio data from the video data.

As described above, the data transmitter 110 according to this embodiment superimposes the previously-processed transmission audio data s201 to which additional information such as the frequency division parameter N and the count value CTS has been added, upon video data, thereby generating the video/audio data superimposed signal s204, and transmits the generated signal s204 to the data receiver 130 via the DVI cable 120.

Next, FIG. 6 is a block diagram illustrating a structure of a data receiver in the digital data transmission system according to this embodiment, and FIG. 7 is a block diagram illustrating components for generating an audio clock in an audio clock generation means of the data receiver.

In FIG. 6, numeral 401 denotes an audio data extraction signal generation means that generates an audio data extraction signal s401 using the horizontal blank sync signal and the pixel clock which are transmitted from the data transmitter 110 via the DVI cable 120, as a timing signal for extracting audio data from the video/audio data superimposed signal s204. Numeral 402 denotes a video/audio data separation means that separates the video/audio data superimposed signal s204 that is inputted through the input terminal 406, into video data and a transmission audio data s201, on the basis of the audio data extraction signal s401 that is outputted from the audio data extraction signal generation means 401 and information indicating the length of audio data, which is added to the transmission audio data s201 by the data transmitter 110. Numeral 403 denotes an audio clock generation means that performs frequency division of the pixel clock that is transmitted from the data transmitter 110 via the DVI cable 120, on the basis of the count value CTS that is added to the transmission audio data s201 by the data transmitter 110, and generates an audio clock s403 by performing phase control. Numeral 404 denotes a data storage means that stores the transmission audio data s201 that has been separated by the video/audio data separation means 402, and outputs the stored transmission audio data s201 in accordance with the audio clock s403 that is outputted from the audio clock generation means 403. Numeral 405 denotes a D/A converter that successively converts the transmission audio data s201 that is outputted from the data storage means 404 into an analog audio signal on the basis of the audio clock s403.

When the horizontal blank sync signal, the pixel clock, and the video/audio data superimposed signal s204 are inputted from the data transmitter 110 to the data receiver 130 having the above-mentioned structure via the DVI cable 120, and the horizontal blank sync signal and the pixel clock are first inputted to the audio data extraction signal generation means 401, the audio data extraction signal generation means 401 starts counting the pixel clock from when receiving the horizontal blank sync signal, and outputs the audio data extraction signal s401 to the video/audio data separation means 402 at a timing when a predetermined count of “n” has been reached.

When the audio data extraction signal s401 that has been generated by the audio data extraction signal generation means 401 is supplied to the video/audio data separation means 402, the video/audio data separation means 402 separates data corresponding to the length of the transmission audio data s201, which is described in the header of the transmission audio data s201, starting from the timing of receipt of the audio data extraction signal s401, from the video/audio data superimposed signal s204, thereby extracting the transmission audio data s201 that is located at the predetermined position in the horizontal blanking interval of the video data. The extracted transmission audio data s201 is temporarily stored in the data storage means 404.

The transmission audio data s201 that has been separated by the video/audio data separation means 402 is transmitted also to the audio clock generation means 403. The audio clock generation means 403 subjects the pixel clock to frequency division by the frequency division parameter N that has been added to the transmission audio data s201 by the data transmitter 110, thereby to generate an audio clock s403.

Components of the audio clock generation means 403 for generating the audio clock will be described with reference to FIG. 7. In FIG. 7, to simplify the figure, flows of data are not shown but only flows of clocks are shown.

The pixel clock that is inputted to the audio clock generation means 403 and the count value CTS as the additional information included in the transmission audio data s201 are inputted to a first frequency division means 501. The first frequency division means 501 subjects the pixel clock to frequency division on the basis of the count value CTS. Then, a frequency division clock s501 having a period that is “CTS” times longer than the pixel clock, which has been obtained by the frequency division of the pixel clock on the basis of the count value CTS, is inputted to a phase control means 506, and phase-controlled in accordance with a phase comparison clock s505 that is generated by the phase control means 506, resulting in an audio clock s403.

The phase control means 506 comprises a phase detector 502 that detects a phase difference between the phase of the inputted frequency division clock s501 and the phase of the phase comparison clock s505 that is generated by a second frequency division means 505, and outputs a control signal on the basis of the phase difference; a low-pass filter 503; a VCO 504 that oscillates the audio clock s403 in accordance with the control signal that is outputted from the phase detector 502; and a second frequency division means 505 that performs frequency division of the audio clock s403 that is oscillated from the VCO 504, using the frequency division parameter N, thereby generating the phase comparison clock s505 corresponding to the transmission audio clock. The phase control means 506 generates the audio clock s403 by generating the control signal in the phase detector 502 on the basis of the phase difference between the phase of the frequency division clock s501 that is generated by the first frequency division means 501 and the phase of the phase comparison clock s505 that is outputted from the second frequency division means 505, and controlling the VCO 504 in accordance with the control signal. In FIG. 7, the frequency division parameter N and the counter value CTS are shown as being inputted to the audio clock generation means 403, while this indicates that the frequency division parameter N and the counter value CTS are inputted with being added to the above-mentioned transmission audio data s201.

Though not shown in FIG. 7, the audio clock s403 that has been generated by the audio clock generation means 403 is thereafter divided to generate a L/R clock and a bit clock. Here, the L/R clock is a sampling clock for audio data, and generally Lch data are transmitted in High sections while Rch data are transmitted in Low sections. The bit clock is synchronized with the L/R clock and used to decide audio data. When data are serially transmitted, the bit clock is utilized. Generally, the bit clock has a frequency that is 64 times or 32 times as high as the sampling frequency, and data of one bit is decided by one clock.

The data storage means 404 outputs the stored audio data s201 to the D/A converter 405, and the audio clock generation means 403 outputs the generated audio clock s403 to the D/A converter 405. The D/A converter 405 receives the digital audio data synchronized with the bit clock, from the data storage means 404, and converts the digital audio data into an analog audio signal using the three kinds of clock signals (the audio clock, the L/R clock, and the bit clock) that have been generated by the audio clock generation means 403.

As described above, the data receiver according to this embodiment receives the pixel clock and the video/audio data superimposed signal s204 from the data transmitter 110 through the DVI cable 120, and performs phase control on the basis of the phase difference between the phase of the frequency division clock s501 that is obtained by performing frequency division of the pixel clock on the basis of the count value CTS included in the transmission audio data that has been superimposed upon the signal s204, and the phase of the phase comparison clock s505 that is obtained by performing frequency division of the audio clock using the frequency division parameter N included in the transmission audio data that has been superimposed upon the signal s204, thereby generating the audio clock s403.

Hereinafter, possible values of the frequency division parameter N will be described in more detail.

The frequency division parameter N takes any value that satisfies the following formula, as is apparent from the construction of the data clock generation means 403 in the above-mentioned data receiver 130. Audio clock×CTS=pixel clock×N  (Formula 1)

where N and CTS are integers.

When the value of the frequency division parameter N that satisfies the above Formula 1 is smaller, the frequency of the phase comparison clock s505 (=the audio clock/N) that is outputted from the second frequency division means 505 in the audio clock generation means 403 becomes higher, and the frequency of the audio clock s403 correspondingly becomes higher, whereby the time required for synchronization pull-in by the audio clock generation means 403 can be favorably reduced, while conversely the generated audio clock s403 includes more jitter, and smooth audio data of high quality cannot be obtained. On the other hand, when the value of the frequency division parameter N is larger, the frequency of the phase comparison clock s505 (=the audio clock/N) that is outputted from the second frequency division means 505 becomes lower, and correspondingly the frequency of the audio clock s403 becomes lower, whereby the synchronization pull-in time in the audio clock generation means 403 adversely gets longer, while conversely the audio clock s403 including less jitter can be generated, and smooth audio data of high quality can be generated.

Thus, in this embodiment, an additional restriction as given by the following Formula 2 is imposed on the possible values of the frequency division parameter N, in addition to the above-mentioned Formula 1. 300 Hz≦audio clock/N≦3000 Hz  (Formula 2)

To be more specific, as shown by Formula 2, when the audio clock/N, i.e., the frequency of the phase comparison clock s505 is set at 300 Hz or higher, the synchronization pull-in time can be made shorter than 100 ms, resulting in an appropriate synchronization pull-in time in the audio clock generation means 403. When the mode of data is changed, i.e., the pixel clock or audio data sampling frequency of data that is transmitted from the data transmitter 110 is changed during transmission or reception of data between devices of the digital data transmission system, the audio clock generation means 403 needs to reestablish the synchronization pull-in. Also in this case, when the frequency of the phase comparison clock s505 is set at 300 Hz or higher as described above, the synchronization pull-in time can be made shorter than 100 ms. Accordingly, the time required to regenerate the audio clock after the change of the mode, and reproduce audio data on the basis of the generated audio clock can be reduced to an appropriate time.

On the other hand, when the frequency of the phase comparison clock s505 (=the audio clock/N) is set at 3000 Hz or lower as shown by Formula 2, high frequency components of clock jitter can be suppressed. Recently, 1-bit D/A converters are commonly employed as the D/A converter because of its high performance and low cost, while these 1-bit D/A converters are easily affected by jitter and require an audio clock including less jitter. In this case, when additional restriction of making the frequency of the phase comparison clock s505 lower than 3000 Hz is added to Formula 1 to suppress the clock jitter, a larger effect can be obtained in the case where the D/A converter 405 reproduces audio data.

FIGS. 8 to 26 show values of the frequency division parameter N, which satisfy the above two formulae for various pixel clocks and various audio data sampling frequencies, and the corresponding count values CTS and frequencies (kHz) of the phase comparison clocks s505, respectively.

FIGS. 8 to 26 are diagrams showing respective possible values of the frequency division parameter N, the count value CTS, and the frequency ref (Hz) of the phase comparison clock, when the pixel clock is 25.2/1.001 MHz, 25.2 MHz, 27 MHZ, 27.1×1.001 MHz, 54 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.001 MHz, and 148 MHz, and the audio data sampling frequency is 32 kHz, 44.1 kHz, and 48 kHz, respectively. The frequency division parameters N shown in FIGS. 8 to 26 are values when the audio clock has a frequency that is 128 times higher than the audio data sampling frequency.

For example, FIG. 8 show the frequency division parameter N, the count value CTS, and the frequency of the phase comparison clock that satisfy the above two formulae in cases where the pixel clock is 25.2/1.001 MHz and the audio data sampling frequency is 32 kHz, 44.1 kHz, and 48 kHz, respectively.

When the 25.2/1.001 MHz pixel clock and the audio clock having the 32 kHz audio data sampling frequency (in this case, a clock having a frequency that is 128 times higher than 32 kHz) are for example inputted to the frequency division parameter decision means 301 in the audio data processing means 201 of the data transmitter 110, the frequency division parameter N can take values as shown in FIG. 8( a) (N=4576, 9152).

While FIGS. 8 to 26 show all possible values of the frequency division parameter N, the count value CTS, and the phase comparison clock frequency (Hz) for various pixel clocks and various audio data sampling frequencies, which satisfy the above two formulae, when the pixel clock is 74.25/1.001 MHz and the audio data sampling frequency is 32 kHz as shown in FIG. 23( a), there is no value that satisfies Formula 2. Therefore, when the pixel clock is 74.25/1.001 MHz and the audio data sampling frequency is 32 kHz, the phase comparison clock frequency 0.176 kHz (N=23296, CTS=421875) is doubled to get the phase comparison clock frequency 0.352 kHz (N=11648, CTS=210937˜210938), thereby making the phase comparison clock frequency higher than 300 Hz. When the count value CTS is calculated according to Formula 1 for the case where the phase comparison clock frequency is 0.352 kHz (N=11648, CTS=210937˜210938), 210937.5 is mathematically derived, but when the counter 303 in the audio data processing means 201 practically counts, it counts up to two count values CTS 210937 and 210938 alternately.

However, when the counter 303 alternately counts up to these two count values CTS (210937 and 210938), jitter is likely to occur in the audio clock that is generated by the data receiver 130. However, since high-quality smooth audio data are needed only in a case where the audio data sampling frequency is at least 96 kHz or 192 kHz that is utilized in a DVD or the like, no problem arises in the case of 32 kHz even when the quality of audio data is somewhat deteriorated.

As describe above, in the digital data transmission system according to this embodiment, the frequency division parameter N that is transmitted together with video data and audio data from the data transmitter 110 to the data receiver 130 can take the values shown in FIGS. 8 to 26. When the digital data transmissions system places importance on reduction of the synchronization pull-in time, it selects a frequency division parameter N that enables the phase comparison clock frequency to be closer to 3000 Hz, and sets the selected parameter N in the frequency division parameter decision means 301 of the audio data processing means 201. When clock jitter is to be suppressed to generate high-quality audio data, a frequency division parameter N that allows the phase comparison clock frequency to be closer to 300 Hz is selected, and the selected parameter is set in the frequency division parameter decision means 301.

In the above descriptions, to decide the frequency division parameter N, Formula 1 is limited by Formula 2, while Formula 1 may be limited by the following Formula 3. Audio clock/N≈1000 Hz  (Formula 3)

When this restriction is imposed, the above-mentioned two effects are simultaneously obtained, i.e., the pull-in time can be reduced and jitter can be suppressed, whereby high-quality audio data can be generated. Specific values of the frequency division parameter N for various pixel clock and various audio data sampling frequency of the case where the restriction of Formula 3 is imposed on Formula 1 are shown in FIGS. 27 and 28, and these values are utilized as recommendation parameters of the frequency division parameter N. FIGS. 27 and 28 are diagrams showing the count value CTS and the frequency (kHz) of the phase comparison clock in the case where the frequency division parameters N are the recommendation parameters.

When a table that gives the recommendation parameters as shown in FIGS. 27 and 28 is provided to the frequency division parameter decision means 301, the frequency division parameter N can be automatically decided on the basis of the pixel clock of video data and the sampling frequency of audio data which are inputted to the data transmitter 110, thereby simplifying the circuit design of the digital data transmission system.

In the above descriptions, the frequency division parameters N that satisfy the audio clock/N≈1000 Hz are utilized as the recommendation parameters, while when the audio data sampling frequency is 44.1 kHz, 88.2 kHz, and 176.4 kHz as shown in FIGS. 27 and 28, the frequency division parameters N that satisfy the audio clock/N≈900 Hz are employed as the recommendation parameters.

The reason is as follows. When the frequency division parameters N that satisfy the audio clock/N≈1000 Hz for example in a case where the audio data sampling frequency is 44.1 kHz are selected from FIGS. 8 to 26, values of the frequency division parameter N as the recommendation parameters vary with pixel clocks as shown in FIG. 29, while when the frequency division parameters N that satisfy the audio clock/N≈900 Hz are utilized for the recommendation parameters as described above, the frequency division parameter N is more likely to take a value N=6272 as shown in FIGS. 27 and 28, thereby obtaining commonality in the frequency division parameter N. When the frequency division parameter N has the commonality, the circuit design of the digital data transmission system is simplified, thereby reducing the device cost.

In the above descriptions, respective possible values of the frequency division parameter N in the cases where the pixel clock are 25.2/1.001 Hz, 25.2 MHz, 27 MHz, 27.1×1.001 MHz, 54 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.001 MHz, and 148 MHz are specifically given, while the pixel clock other than these values may be inputted to this digital data transmission system. In such cases, the frequency division parameters that are given in Column “others” of FIGS. 27 and 28 are utilized. These values of the frequency division parameter N in Column “others” are values having a high commonality among the frequency division parameters N as the recommendation parameters which are shown for each audio data sampling frequency (for example, when the audio data sampling frequency is 32 kHz the frequency division parameter N is 4096, and when the audio data sampling frequency is 44.1 kHz the frequency division parameter N is 6272). When there values are utilized, occurrence of jitter can be suppressed and high-quality audio data can be generated even when the pixel clock other than the aforementioned clocks is inputted to the digital data transmission system. Further, the circuit design is simplified, whereby the device cost can be reduced.

As described above, according to this embodiment, the data transmitter 110 transmits, to the data receiver 130, a video/audio data superimposed signal s204 that is obtained by superimposing audio data on a horizontal blanking interval of video data in a superimposition timing that is generated using a horizontal blank sync signal and a pixel clock, together with the horizontal blank sync signal and the pixel clock, via the DVI cable 120, and then the data receiver 130 generates a timing signal that is employed for extracting audio data from the video/audio data superimposed signal s204, using the transmitted horizontal blank sync signal and pixel clock, and separates the video/audio data superimposed signal s204 into video data and audio data using the generated timing signal, and converts the digital audio data into an analog audio signal using an audio clock that is generated by dividing the pixel clock. Therefore, audio data can be transmitted easily and satisfactorily using the existing interface for transmitting video data. That is, audio data can be transmitted through the same cable as that for video data, utilizing the existing digital video data transmission system that is standardized as the DVI standard. More particularly, in this embodiment, the video data transmission processing is carried out as conventionally, while the timing signal is generated using the horizontal blank sync signal and the pixel clock, and the superimposition and separation of audio data is performed using the generated timing signal. Therefore, there is no need to change the conventional DVI system in the structure for transmitting video data, and the processing blocks for video data that are prepared for the DVI system can be used as they are both on the transmitting end and the receiving end.

Further, in this embodiment, the audio clock is generated in the data receiver 130 on the basis of the frequency division parameter N that is decided based on the pixel clock of video data and the sampling frequency of audio data which are inputted in the data transmitter 110, and the count value CTS that is obtained by counting the period of the audio clock that has been subjected to frequency division with the frequency division parameter N, with the pixel clock, and the range of the frequency division parameter N is set at 300 Hz≦audio clock/N≦3000 Hz. Therefore, the synchronization pull-in time required for the data receiver 130 to generate the audio clock s403 can be limited within 100 ms, and the high frequency components of clock jitter can be suppressed, thereby generating high-quality audio data.

In the above-mentioned embodiment, the audio clock has a frequency that is 128 times higher than the audio data sampling frequency. However, the audio clock may have a frequency that is, for example, 256 times or 384 times higher than the sampling frequency. When the audio clock is 256 times higher than the sampling frequency, the frequency division parameter N takes values that are one half the values of the frequency division parameter N shown in FIGS. 8 to 29 (i.e., N/2). When the audio clock is 386 times higher than the sampling frequency, the frequency division parameter N takes values that are one third of N (i.e., N/3).

In this embodiment, the timing signal is generated using the horizontal blank sync signal and the pixel clock, and audio data is superimposed at a predetermined position in the horizontal blanking interval of video data using the generated timing signal. However, the timing signal can be generated using a vertical blank sync signal and the pixel clock, and audio data can be superimposed at a predetermined position in a vertical blanking interval of video data using the generated timing signal.

In the above-mentioned embodiment, the data transmitter transmits digital audio data of one channel, while the present invention can apply to cases where the data transmitter transmits digital audio data of two channels, or digital data of three or more channels.

Further, in this embodiment, the data transmitter transmits packets in which audio data of the predetermined sampling rate is included, while the data transmitter can transmit packets including digital audio data that has been compressively encoded by a predetermined method (for example, AC3 method or AAC method).

In this embodiment, audio data is superimposed upon video data and the superimposed data is transmitted through the DVI standard transmission line, while other video data transmission standards may be utilized. In such case, a transmission line that implements wireless transmission as well as a transmission line that is connected with a wired cable can be employed.

INDUSTRIAL AVAILABILITY

The data transmitter and the data receiver according to the present invention are greatly useful in realizing a data transmitter and a data receiver that transmits video data and audio data that are outputted from a video/audio signal source such as a videocassette tape recorder/player, a video disk player, and a tuner, to a display unit such as a monitor receiver having a sound output function, or a television receiver, through one transmission cable, and reproduces video data and audio data easily and satisfactorily on the receiving end. 

1. A data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, said data processing unit including, a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generating the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and said transmission audio clock being a clock having a frequency of 300 Hz or higher.
 2. A data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, said data processing unit including, a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock that has been generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generating the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and said transmission audio clock being a clock having a frequency of 3000 Hz or lower.
 3. A data transmitter that transmits video/audio data through a digital display connecting interface, including: a data processing unit for processing audio data to output transmission audio data; and a data superimposing unit for superimposing the transmission audio data upon video data to output video/audio data, said data processing unit including, a frequency dividing means for frequency dividing an audio clock as a reference clock for the audio data using a predetermined frequency division parameter N, to generate a transmission audio clock having a period that is N times longer than the audio clock; and a count means for counting the period of the transmission audio clock that has been generated by the frequency dividing means with utilizing a pixel clock as a reference clock for the video data to output the count value CTS, and generating the transmission audio data by adding additional information including the frequency division parameter N and the count value CTS to the audio data, and said transmission audio clock being a clock having a frequency that is 300 Hz or higher, and 3000 Hz or lower.
 4. The data transmitter of claim 3 wherein when the pixel clock is 25.2/1.001 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 5. The data transmitter of claim 3 wherein when the pixel clock is 25.2/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 6. The data transmitter of claim 3 wherein when the pixel clock is 25.2/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 7. The data transmitter of claim 3 wherein when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 8. The data transmitter of claim 3 wherein when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 9. The data transmitter of claim 3 wherein when the pixel clock is 25.2 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 10. The data transmitter of claim 3 wherein when the pixel clock is 27 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 11. The data transmitter of claim 3 wherein when the pixel clock is 27 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 12. The data transmitter of claim 3 wherein when the pixel clock is 27 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 13. The data transmitter of claim 3 wherein when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 14. The data transmitter of claim 3 wherein when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 15. The data transmitter of claim 3 wherein when the pixel clock is 27×1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 16. The data transmitter of claim 3 wherein when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 17. The data transmitter of claim 3 wherein when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 18. The data transmitter of claim 3 wherein when the pixel clock is 54.0 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 19. The data transmitter of claim 3 wherein when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 32 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=11648 and 210937≦CTS≦210938.
 20. The data transmitter of claim 3 wherein when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=17836 and CTS=234375.
 21. The data transmitter of claim 3 wherein when the pixel clock is 74.25/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the relationship between the frequency division parameter N (N is an integer) and the count value CTS (CTS is an integer) is N=11648 and CTS=140625.
 22. The data transmitter of claim 3 wherein when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 23. The data transmitter of claim 3 wherein when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 24. The data transmitter of claim 3 wherein when the pixel clock is 74.25 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 25. The data transmitter of claim 3 wherein when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 26. The data transmitter of claim 3 wherein when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 27. The data transmitter of claim 3 wherein when the pixel clock is 148.5/1.001 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 28. The data transmitter of claim 3 wherein when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 32 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 29. The data transmitter of claim 3 wherein when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 44.1 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 30. The data transmitter of claim 3 wherein when the pixel clock is 148.5 MHz and the data sampling frequency of audio data is 48 kHz, the frequency division parameter N (N is an integer) and the count value CTS is an integer.
 31. A data receiver that receives video/audio data through a digital display connecting interface, including: a video/audio data separating unit for separating video data and transmission audio data from the video/audio data; and an audio clock generating unit for generating an audio clock as a reference clock for audio data, on the basis of a pixel clock as a reference clock for the video data and a frequency division parameter N that has been added to the transmission audio data, said audio clock generating unit including: an oscillator that oscillates the audio clock in accordance with a control signal; a frequency dividing means for frequency dividing the pixel clock using a count value CTS included in the transmission audio data to generate a frequency division clock having a period that is CTS times longer than the pixel clock; and a phase control means for controlling the oscillator in accordance with the control signal that is generated on the basis of a difference in phase between the frequency division clock and a phase comparison clock that is obtained by dividing the audio clock by a frequency division parameter N.
 32. The data receiver of claim 31 wherein the phase control means controls the oscillator on the basis of a difference in phase between the frequency division clock that is generated by the frequency dividing means and the phase comparison clock having a frequency that is nearest to 1000 Hz.
 33. The data receiver of claim 31 wherein when the sampling frequency for the audio data is 44.1 kHz, the phase control means controls the oscillator on the basis of a difference in phase between the frequency division clock that is generated by the frequency dividing means, and the phase comparison clock having a frequency that is nearest to 900 Hz.
 34. The data receiver of claim 31 wherein when the data sampling frequency of the audio data is 32 kHz or 48 kHz, and the pixel clock has a frequency other than 25.2/1.001 MHz, 25.022 MHz, 27.000 MHz, 27.0×1.001 MHz, 54.000 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.001 MHz, and 148.5 MHz, the frequency division parameter N (N is an integer) is decided such that the phase comparison clock that is obtained by dividing the pixel clock by the frequency division parameter N has a frequency nearest to 1000 Hz.
 35. The data receiver of claim 31 wherein when the data sampling frequency of the audio data is 44.1 kHz, and the pixel clock has a frequency other than 25.2/1.001 MHz, 25.022 MHz, 27.000 MHz, 27.0×1.001 MHz, 54.000 MHz, 74.25/1.001 MHz, 74.25 MHz, 148.5/1.001 MHz, and 148.5 MHz, the frequency division parameter N (N is an integer) is decided such that the phase comparison clock that is obtained by dividing the pixel clock by the frequency division parameter N has a frequency that is the nearest to 900 Hz. 